There are several tools that allow the engineer to both model and measure power in an application. If possible, this measurement should be viewed graphically in a data vs. The engineer should measure from the CPU core area as well as from the peripheral I/O area. During this phase, the engineer should use the appropriate power measurement techniques and tools measure and analyze power at the core system level. In the analyze and tune phase of the life cycle the engineer wants to see what they have and possibly go back and tune it according to feedback.
Power manager 2000 software#
Once the DSP engineer has captured the plan and the power consumed, and implemented the code and the power scaling library as well as the OS power manager and power-efficient software with the application, the next phase is to measure results ( Figure 7.20).
Power manager 2000 registration#
5Ĭoordinating sleep and scaling – The engineer can coordinate sleep modes and V/F scaling using registration and notification mechanisms provided by the PWRM module. These can be set statically or at run-time. Using sleep modes – The engineer can set custom sleep modes to save power during inactivity. Since power usage is linearly proportional to the frequency and quadratically proportional to the voltage, using the PWRM module can result in significant power savings. Scaling voltage and frequency – The engineer can dynamically change the operating voltage and frequency of the CPU.
This function can idle power-using peripherals as desired. Saving power at boot time – This allows the engineer to specify a power-saving function to be called automatically at boot time. Idle clock domains – The engineer can idle specific clock domains to reduce active power consumption. The power scaling libraries, which can be developed, purchased, or otherwise obtained, allow for supporting scaling of the frequency as well scaling of the voltage on these devices and provide query options for frequency voltage, scaling latencies, and other kinds of things that relate to the actual operating mode and the transitioning between your modes for power-efficient performance and callbacks, before and after scaling operations that accommodate these types of applications.Īt a minimum, the combined capability of a power scaling library and a power manager software component provides the DSP engineer the ability to: 1 The combination of software at this phase that supports the coding and building of the application are chip specific power scaling libraries and a power aware OS manager. At this phase, in order to utilize the appropriate level of power optimization techniques, the engineer should look for OS support for power and frequency tuning. This is the level of abstraction the engineering team will be programming to. At this phase of the application development life cycle, the engineer is making a decision on the operating system. The next phase of the power optimization life cycle is code and build ( Figure 7.19).
Power manager 2000 trial#
A detailed power spreadsheet provides for very easy trial configurations and allows the engineer to configure it however they feel they will configure their device as well as apply loads, however they wish to load their application to get a reasonably close proxy of what the power consumption will be for their design. With information at this level of detail, the engineer can plan the application net power consumption according to the utilization functions on the device. These should provide detailed chip-specific internal function power as well as peripheral function power and other detailed data of operating power and standby power. The goal is to find or otherwise develop detailed device-specific spreadsheets. This can be done by looking at device specification sheets or a more detailed analysis of the application as it relates to the device. During this phase, the engineer will be comparing power numbers at the device level. In the application design phase, the engineer will be choosing the device to use in the application as well as performing some high level application design steps. Power planning during the application design phase (courtesy of Texas Instruments)
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